1. Field of the Invention
The present invention generally relates to the art of electronics and more particularly relates to an analog multiplier-divider.
2. Description of the Prior Art
There are many uses of analog multiplier-dividers in modem electronics. Multiplier-dividers produce an output signal that is proportional to a ratio of two or more input signals. The input and output signals can either be voltages or currents.
One common use for multiplier-dividers is in power factor correction (PFC) circuits. PFC circuits commonly use multiplier-dividers to generate a control signal based on an input current, a feedback signal, and an input voltage. Other uses of multiplier-divider circuits include but are not limited to automatic gain control (AGC) circuits.
There are many known ways of constructing analog multiplier-dividers, such as logarithmic amplifiers and antilog amplifiers. The implementation of a logarithmic amplifier normally uses the p-n junction volt-ampere characteristic; it is given by
ID=I0xc3x97[exp(VD/xcex7VT)xe2x88x921]xe2x80x83xe2x80x83(1)
where I0 is the reverse saturation current; VD is the forward bias voltage; xcex7 is the constant; VT=T/11,600 and T is the temperature xc2x0 K. Since the output current ID is the exponential function of the forward bias voltage VD, the linear operating region is small. The book xe2x80x9cAnalog Integrated Circuit Designxe2x80x9d by David A. Johns and Ken Martin (1997, p 366-367) teaches another known analog multiplier-divider. This particular multiplier-divider is also implemented by using p-n junction devices. As FIG. 1 shows, it is referred to as a four-quadrant multiplier.
The prior-art multiplier-divider shown in FIG. 1 is built using bipolar transistor devices. It supplies an output current with the amplitude that is proportional to the product of a first input current and a current ratio. The current ratio is equal to the amplitude of a second input current divided by the amplitude of a bias current.
Many other known prior-art multiplier-dividers are all based on the principles as the prior-art multiplier-divider shown in FIG. 1. Those prior-art multiplier-dividers share the same disadvantages because they are built using bipolar transistor devices.
One disadvantage of the prior-art multiplier-divider shown in FIG. 1 is its high manufacture cost. For many present-day applications, such as PFC circuits, integrated circuits manufacture using bipolar process are not suitable because bipolar devices still occupy lots of die space and increase the cost.
Another disadvantage of the prior-art multiplier-divider shown in FIG. 1 is that the output of the circuit varies significantly with temperature. Referring to equation (1), it is obviously that bipolar devices have high temperature coefficients. Thus, the output of the circuit is highly susceptible to temperature changes.
Another disadvantage of the prior-art multiplier-divider shown in FIG. 1 is high power consumption. The prior-art multiplier-divider requires a constant non-zero biasing current to operate bipolar transistors in linear mode. This results in significant power consumption.
Another disadvantage of the prior-art multiplier-divider shown in FIG. 1 is poor noise immunity. This is because the prior-art multiplier-divider uses high-gain bipolar transistor devices. With such devices, even relatively small input signal distortion can result in significant output signal distortion.
Another disadvantage of the prior-art multiplier-divider of FIG. 1 is that it has a narrow input range, limited to the linear operating region of bipolar transistors. Outside this narrow input signal range, the multiplier-divider shown in FIG. 1 is highly susceptible to distortion.
Therefore, it is needed to improve the drawbacks of the prior-art multiplier-dividers. In particular, an improved multiplier-divider that has a smaller die size while being suitable for a wider range of operating temperatures is absolutely needed.
According to one aspect of the present invention, the multiplier-divider of the present invention produces an output signal in response to three input signals. The output signal is proportional to the product of a first input signal and a second input signal divided by a third input signal.
A general objective of the present invention is to provide a general-purpose multiplier-divider. It is a further objective of the present invention to provide a multiplier-divider that is suitable to apply in a power factor correction (PFC) circuit of a switch mode power supply.
Another objective of the present invention is to provide a multiplier-divider that is manufactured in CMOS process. The multiplier-divider according to the present invention exclusively uses MOSFET-based devices. Therefore, the multiplier-divider according to the present invention can be manufactured at a significantly reduced die-size level, and at a lower cost than the prior-art multiplier-divider.
Another objective of the present invention is to provide a multiplier-divider having a characteristic equation that is substantially independent of temperature, compared to prior-art multiplier-dividers.
Another objective of the present invention is to provide a multiplier-divider with reduced power consumption. The multiplier-divider according to the present invention does not require a constant biasing current.
Another objective of the present invention is to provide a multiplier-divider with improved noise immunity. The accuracy of the output signal of the multiplier-divider according to the present invention is not significantly affected by small noise components from the input signals.
Briefly, the present invention relates to a switched charge multiplier-divider. The switched charge multiplier-divider is built according to the principle of capacitor charge theory. The voltage across the capacitor is proportional to the product of the charge current and the charge time interval, and is divided by the capacitance of the capacitor. By using a modulated charge current and a programmable charge time to switch the capacitor, the voltage across the capacitor can be controlled. This capacitor voltage is the output voltage of the switched charge multiplier-divider.
The switched charge multiplier-divider according to the present invention can perform signal multiplication and division. Use of the capacitor charge technique enables the implementation of a multiplier-divider with reduced power consumption, improved noise immunity, a wider operating range, and a lower temperature coefficient.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.